In a DRAM multiple-bit-level storage design described in U.S. Pat. No. 5,283,761, invented by Peter Gillingham, memory cell charge is dumped onto a bitline to create a data voltage which is sensed as to whether it is above or below a voltage level midway between a highest and a lowest of four levels (providing the sign bit), and the voltage on a reference bitline is set to be higher than the lowest and lower than the next highest of the four levels in the event the data voltage is below the midway voltage level, and set to a voltage higher than the second highest and lower than the highest of the four levels in the event the data voltage is above the midway point. The data voltage is then sensed as to whether it is higher or lower in voltage than the reference bitline (providing the magnitude bit), whereby which of the four levels the data bit occupies is read.
That design is dependent on the reference value being set based on the conditional value of a magnitude bit. To restore the charge to the memory cell, either a full logic level is written to the cell, or an attenuated version thereof, depending on whether the data voltage was either the highest or lowest, or the second lowest or second highest values respectively. This required a circuit which attenuated a voltage conditionally based on the value of sensed data. Such a circuit is difficult to implement in the tight pitch of a DRAM sense amplifier.
The description of U.S. Pat. No. 5,283,761 is incorporated herein by reference.